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explore microelectronics reserves the right to make changes without further notice to any products herein to improve reliabilit y, function or design. explore microelectronics does not assume any liability arising out of the a pplication or use of any product or circuit described herein; neither does it convey any license u nder its patent rights nor the rights of others. explore microele ctronics products are not designed, int ended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other applicat ion in which the failure of the explore microelectronics product could create a situation where persona l injury or death may occur. should buyer purchase or use explore microelectronics products for any such unintended or unauthorized application, buyer s hall indemnify and hold explore microelectronics and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, da mages, and expenses, and reasonable attorney fees ar ising out of, directly or indirectly, any claim of personal injury or death associ ated with such unintended or unauthorized use, even if such claim alle ges that explore microelectroni cs was negligent regarding the design or manufacture of the part. user guide ? EP387A_ug v0.7 explore microelectronics 1 dual pixel lvds transmitter EP387A user guide v0.7 original release da te: january 30, 2003 explore microel ectronics, taiwan revise d: nov. 29, 2005 free datasheet http://www.datasheetlist.com/
user guide ? EP387A_ug v0.7 explore microelectronics 2 revision history version number revision date author description of changes 0.0 jan/30/2003 -- initial version 0.1 feb/18/2003 -- correct pin names 0.2 jun/17/2003 -- power consumption measurement 0.3 aug/14/2003 -- correct ambiguous sentence 0.4 dec/14/2004 ether lai update electrical characteristics & add package information 0.5 jun/02/2005 ether lai additional function in 2nd link; id position change 0.6 jul/15/2005 ether lai add esd rating 0.7 nov/29/2005 ether lai change package marking free datasheet http://www.datasheetlist.com/
user guide ? EP387A_ug v0.7 explore microelectronics 3 section 1 introduction 1.1 overview the EP387A supports dual lvds links transmission between the host a nd the flat panel display up to qxga resolutions. the transmitter conve rts 48 bits (24-bit color, dual pixel) of cmos/ttl data and 3 control bits into 8 lvds (low voltage differential signal) data streams. at a maximum input clock rate of 112mhz in the dual pixel mode , each lvds differential data pair speed is 7 84mbps, providing a total throughput of 5.4gbps. two additional m odes are supported. one of them converts 24 bits (24-bit color, single pixel) data input into dual lvds links and the input clock rate can be up to 165mhz. the other mode converts 24 bits data input into single lvds li nk in order to support the inter-operability with the conventional lvds applicat ion. the configurable pre- emphasis feature is provi ded to support additional output strength to reduce the cable loading effects. the EP387A pr ovides a second lvds output clock pair. both lvds clocks pairs are id entical. this feature suppor ts backward compatibility with the previous generation of single pixel l vds transmitter. the second clock allows the transmitter to interface to panel using a "dual pixel" configuration of two 24-bit or 18-bi t lvds receivers. 1.2 features the EP387A includes the following distinctive features: ? supports svga through qxga resolutions ? support 32.5mhz to 112/170mhz clock rates ? up to 5.4gbps bandwidth ? pre-emphasis reduces cable loading effects ? programmable interface to timing controll er, dual-in/dual-out, si ngle-in/dual-out and single-in/single-out. ? cycle-to-cycle jitter rejection ? 5v tolerant on data and control input pins ? programmable data and control strobe select ? compatible with ansi/t ia/eia-644 lvds standard ? compatible with national ds90c387a ? single 3.3v cmos design ? 100-pin lqfp (pb free, complia nt to jedec/ipc j-std-006) free datasheet http://www.datasheetlist.com/
user guide ? EP387A_ug v0.7 explore microelectronics 4 free datasheet http://www.datasheetlist.com/
user guide ? EP387A_ug v0.7 explore microelectronics 5 section 2 overview 2.1 block diagram figure 2-1 block diagram of lvds transmitter EP387A dclk r17 - r10 g17 - g10 b17 - b10 ttl input latch pll a0 hsync, vsync, de r_fb, r_fde, dual r27 - r20 g27 - g20 b27 - b20 pwr_up data serializer 48 a1 a2 a3 a4 a5 a6 a7 clk1 clk2 vcc pre pllsel free datasheet http://www.datasheetlist.com/
user guide ? EP387A_ug v0.7 explore microelectronics 6 2.2 pin diagram figure 2-2 pgnd 16 nc 15 pre 14 gnd 13 pvdd 12 dclk 11 r10 10 r11 9 r12 8 r13 7 r14 6 r15 5 r16 4 r17 3 g10 2 g11 1 clk2p 26 clk2m 27 a7p 28 a7m 29 lvdd 30 a6p 31 a6m 32 a5p 33 a5m 34 lgnd 35 a4p 36 a4m 37 a3p 38 a3m 39 lvdd 40 clk1p 41 lgnd 25 gnd 24 dual 23 pwr_up 22 r_fde 21 r_fb 20 pgnd 19 pvdd 18 pgnd 17 clk1m 42 lgnd 43 a2p 44 a2m 45 a1p 46 a1m 47 lvdd 48 a0p 49 a0m 50 b24 60 b23 61 b22 62 b21 63 b20 64 g27 65 g26 66 vdd 67 gnd 68 g25 69 g24 70 g23 71 g22 72 g21 73 g20 74 r27 75 lgnd 51 gnd 52 vdd 53 hsync 54 vsync 55 de 56 b27 57 b26 58 b25 59 g12 100 g13 99 gnd 98 vdd 97 g14 96 g15 95 g16 94 g17 93 b10 92 b11 91 b12 90 b13 89 b14 88 b15 87 b16 86 b17 85 r20 84 gnd 83 vdd 82 r21 81 r22 80 r23 79 r24 78 r25 77 r26 76 pin diagram of EP387A lvds transmitter free datasheet http://www.datasheetlist.com/
user guide ? EP387A_ug v0.7 explore microelectronics 7 2.3 pin description unless otherwise stated, unus ed input pins must be tied to ground, and unused output pins left open. table 2-1 input co ntrol/data/clk pins name pin # in/out description r17~r10 g17~g10 b17~b10 3~10 93~96,99~ 100, 1, 2 85~92 in pixel data inputs for dual pixel input mode or single pixel input mode. r27~r20 g27~g20 b27~b20 75~81, 84 65~66,69~ 74 57~64 in pixel data inputs for dual pixel input mode. de 56 in data enable input. hsync 54 in horizontal sync input. vsync 55 in vertical sync input. dclk 11 in data clock input. r_fb 20 in programmable data strobe select. rising data strobe edge selected when input is high. r_fde 21 in programmable de strobe select. tied high for data active when de is high. nc 15 in not used. pre 14 in pre-emphasis level select. pre-emphasis is active when input is tied to vdd through external pull-up resistor. resistor value determines pre-emphasis level. for normal lvds drive level, leave this pin open (do not tie to ground). dual 23 in three modes selectable from this pin configuration. 1. dual pixel in, dual link out (dual = vdd) 2. single pixel in, dual link out (dual = 1/2 vdd) 3. single pixel in, single link out (dual = gnd). only lvds channels a0 thru a3 and clk1 are active for power saving. pwr_up 22 in power up. table 2-2 lvds output pins name pin # in/out description anp 28, 31, 33, 36, 38, 44, 46, 49 out positive lvds differential data output. anm 29, 32, 34, 37, 39, 45, 47, 50 out negative lvds differential data output. clk1p 41 out positive lvds differential clock output. clk1m 42 out negative lvds differential clock output. clk2p 26 out additional positive lvds differential cl ock output. identical to clk1p. no connect if not used. clk2m 27 out additional negative lvds differential clock output. identical to clk1m. no connect if not used. free datasheet http://www.datasheetlist.com/
table 2-3 power and ground pins name pin # in/out description vdd 53, 67, 82, 97 pwr digital vdd, 3.3v vss 13, 24, 52, 68, 83, 98 gnd digital ground. lvdd 30, 40, 48 pwr analog vdd, 3.3v lgnd 25, 35, 43 gnd analog ground. pvdd 12, 18 pwr pll vdd, 3.3v pvss 16, 17, 19 gnd pll ground. user guide ? EP387A_ug v0.7 explore microelectronics 8 free datasheet http://www.datasheetlist.com/
user guide ? EP387A_ug v0.7 explore microelectronics 9 2.4 electrical characteristics absolute maximum conditions symbol parameter min typ max units vcc supply voltage -0.3 4.0 v v i input voltage -0.3 v cc + 0.3 v v o output voltage -0.3 v cc + 0.3 v v od lvds driver output voltage -0.3 v cc + 0.3 v t j junction temperature -25 125 t stg storage temperature -65 150 ja thermal resistance (junction to ambient) 49 esd human body model (mil-std-883f 3015.7) 3 kv 1. permanent device damage may occur if absolute maximum conditions are exceeded. 2. functional operation should be restricted to the conditions described under normal operating conditions. normal operating conditions symbol parameter min typ max units vcc supply voltage 3.0 3.3 3.6 v v ccn supply voltage noise 100 mv p-p t a ambient temperature (with power applied) -10 25 70 cmos/ttl dc specifications ( under normal operating conditions unless otherwise specified ) symbol parameter conditions min typ max units v ih high-level input voltage 2.0 vcc v v il low-level input voltage gnd 0.8 v i inc input current 0 <= v in <= vcc +/- 10 ua free datasheet http://www.datasheetlist.com/
user guide ? EP387A_ug v0.7 explore microelectronics 10 lvds transmitter dc specifications ( under normal operating conditions unless otherwise specified ) symbol parameter conditions min typ max units v od differential output voltage r l = 100 ? 250 350 450 mv ? v od change in v od between complimentary output states 35 mv v oc common mode voltage 1.125 1.25 1.375 v ? v oc change in v oc between complimentary output states 35 mv i os output short circuit current v out = 0v, r l = 100 ? -10 ma i oz output tri-state current pwr_up = 0v, v out = 0v or vcc +/- 1 +/- 10 ua supply current ( under normal operating conditions unless otherwise specified ) symbol parameter conditions min typ max units i tccg transmitter supply current worst case r l = 100 ?, c l = 5 pf, worst case pattern, dual = vcc f = 32.5 mhz 48 ma f = 67.5 mhz 65 ma f = 82.5 mhz 72 ma f = 112 mhz 96 ma transmitter supply current 16 grayscale r l = 100 ?, c l = 5 pf, 16 grayscale pattern, dual = vcc f = 32.5 mhz 42 ma f = 67.5 mhz 54 ma f = 82.5 mhz 58 ma f = 112 mhz 75 ma i tccz transmitter supply current power down pwr_up = 0, input source is tri-stated 28 ua free datasheet http://www.datasheetlist.com/
user guide ? EP387A_ug v0.7 explore microelectronics 11 figure 2-3 worst case pattern t r2x, g2x, b2x, x = 0 ~ 7 r1x, g1x, b1x, x = 0 ~ 7 dclk figure 2-4 16 grayscale pattern dclk frequency f f/16 f/8 f/4 f/2 steady state, low r10/r20, g10/g20, b10/b20 r11/r21, g11/g21, b11/b21 r12/r22, g12/g22, b12/b22 r13/r23, g13/g23, b13/b23 other data inputs de, hsync, vsync steady state, high free datasheet http://www.datasheetlist.com/
user guide ? EP387A_ug v0.7 explore microelectronics 12 recommended transmitter input characteristics symbol parameter conditions min typ max units t cit dclk in transition time dual = gnd or vcc 1.0 2.0 3.0 ns dual = 1/2 vcc 1.0 1.5 1.7 ns t cip dclk in period dual = gnd or vcc 8.928 30.77 ns dual = 1/2 vcc 5.88 15.38 ns t tch dclk in high time 0.35t 0.5t 0.65t ns t tcl dclk in low time 0.35t 0.5t 0.65t ns transmitter ac specifications ( under normal operating conditions unless otherwise specified ) symbol parameter conditions min typ max units t llht lvds low-to-high transition time pre = 0.75v 0.14 0.7 ns pre = vcc 0.11 0.6 ns t lhlt lvds high-to-low transition time pre = 0.75v 0.16 0.8 ns pre = vcc 0.11 0.7 ns t ts ttl data setup to dclk in 3.0 ns t th ttl data hold from dclk in 0 ns t plls pll set time 10 ms t pdo power down delay 100 ns free datasheet http://www.datasheetlist.com/
user guide ? EP387A_ug v0.7 explore microelectronics 13 2.5 timing diagrams figure 2-5 lvds ou tput timing definition t llht 5pf t lhlt 20% 20% 80% 80% ta+ v diff = (ta+) - (ta-) 100 : ta- v diff figure 2-6 ttl input timing definition t cit t cit 10% 10% 90% 90% dclk in 0v 3v figure 2-7 setup/hold an d high/low timing definiti on (falling edge strobe) t cip dclk in rxn, gxn, bxn 1.5 v 1.5 v 2.0v 2.0v 2.0v 0.8v 0.8v t tcl t tch t th t ts figure 2-8 phase lock loo p set time definition pwr_up vcc 3.0v 3.0v dclk in clk1(2) p/m vdiff = t plls tri-state free datasheet http://www.datasheetlist.com/
user guide ? EP387A_ug v0.7 explore microelectronics 14 figure 2-9 power down delay timing definition pwr_up 1.5v dclk in axp, axm t pdo tri_state free datasheet http://www.datasheetlist.com/
user guide ? EP387A_ug v0.7 explore microelectronics 15 2.6 lvds outputs / ttl data inputs mapping the lvds clock waveshape is shown in the following fi gure. note that the rising edge of the lvds clock occurs two lvds sub symbols before the current cycl e of data. the clock is composed of a 4 lvds sub symbol high time and a 3 lvds sub symbol low time. the respective pin names are shown in the figure and these names are not the color mapping information but pin names only. input b17 and b 27 are double wide bits. the de si gnal is mapped to two lvds sub symbols and two lvds clocks are pr ovided for the backward compatibil ity. also, there ar e two reserved bits and their corresponding receiver outputs has to be left open. r11? r10? a0 +/- clk1 +/- clk2 +/- g10 r15 r14 r13 r12 r11 r10 g12? g11? a1 +/- b11 b10 g15 g14 g13 g12 g11 b13? b12? a2 +/- de vs hs b15 b14 b13 b12 r17? r16? a3 +/- b17 b16 g17 g16 r17 r16 r21? r20? a4 +/- g20 r25 r24 r23 r22 r21 r20 g22? g21? a5 +/- b21 b20 g25 g24 g23 g22 g21 b23? b22? a6 +/- de vs * hs * b25 b24 b23 b22 r27? r26? a7 +/- b27 b26 g27 g26 r27 r26 previous cycle current cycle 1 figure 2-10 lvds outputs / ttl inputs data mapping notes : 1. * means "valid for the new design (contact sales for more details)" free datasheet http://www.datasheetlist.com/
user guide ? EP387A_ug v0.7 explore microelectronics 16 2.7 functional descriptions the EP387A is designed to re ject cycle-to-cycle jitter which may be seen at the input clock. very low cycle-to-cycle jitter is passed on to the transmitter outputs. this signifi cantly reduces the impact of jitter provided by the input clock source and improve the accuracy of data sampling. the EP387A offers the progra mmable edge data st robes selection for convenient interface with a variety of the graphic controllers. the diff erent edge strobe can be programmed for rising edge strobe or falling edge strobe through a dedicated pin. a rising edge strobed transmitter will inter-operate with a falling edge receiver without any translation logic. pre-emphasis adds extra current dur ing lvds logic transition to reduce the additional cable loading effects. pre-empha sis strength is set via a dc voltage level a pplied from min to max (0.75v to vcc) at the "pre" pin. a higher input voltage on the "pre" pi n increases the magnitude of the dynamic current during data transition. the "pre" pin requires one exte rnal pull-up resistor to vcc in order to set the expected dc level. there is an internal resistor netw ork, which cause a voltage drop. refer to the following table to set th e expected voltage level. table 2-4 pre-emphasis dc voltage level setting external resistor in pre resulting voltage effects 1m-ohm or nc 0.75v standard lvds 50k-ohm 1.0v 9k-ohm 1.5v 50% pre-emphasis 3k-ohm 2.0v 1k-ohm 2.6v 100 ohm vcc 100% pre-emphasis the EP387A can be configured to different operating modes: 1. dual pixel input, dual lvds output 2. single pixel input, single lvds output 3. single pixel input, dual lvds output the first "dual-in, dual-out" mode can be selected by applying vcc to the control pin "dual". in dual mode, the transmitter outputs two lvds clock in orde r to drive the traditional single-channel receiver. the second "single-in, single-out" m ode can be selected by applying gn d to the control pin "dual". in single mode, the lvds output data pairs "a4" to "a7" and the lvds clock pairs "clk2" are disabled to reduce the power dissipation. the third "single-in, dual-out" mode can be selected by applying 1/2vcc (1.65v) level to the control pin "dual". in this mode, the input signals are splitted into odd and even pixel star ting with the odd (first) pixel outputs to "a0" -- "a 3" pairs and the next even (second) pixe l outputs to "a4" -- "a7" pairs. the splitting of the data signals also starts with de (data enable) tran sitioning from logic low to high indicating active da ta. the "r_fde" pin must be set high in this case. the number of clock cycles during blanking time must be even number. free datasheet http://www.datasheetlist.com/
user guide ? EP387A_ug v0.7 explore microelectronics 17 the following table provides the summ ary of the possible operating modes: table 2-5 summary of the op erating mode configuration pin condition operating mode r_fb r_fb = vcc rising edge input data strobe r_fb = gnd falling edge input data strobe r_fde r_fde = vcc active data de = high r_fde = gnd active data de = low dual dual = vcc dual pixel input, dual lvds output dual = gnd single pixel input, single lvds output dual = 1/2 vcc single pixel input, dual lvds output the transmitter provides the power dow n feature in order to save the to tal system power. when the power down feature enabled, the current draw from the supply pins is mini mized and the plls are shut down. the lvds outputs are tri-stated. this feature is enabled by setting the pwr_up pin to low. this pin should be driven high to enable th e device once applied vcc is stable. free datasheet http://www.datasheetlist.com/
user guide ? EP387A_ug v0.7 explore microelectronics 18 2.8 package ident pin1 EP387Apbf 14.0 typ 16.0 typ 1.6 max 1.4 typ 0.5 typ 0.22 typ units: mm 100 100 pin lqfp (pb free, compliant to jedec/ipc j-std-006) date code date code : yyww lot number free datasheet http://www.datasheetlist.com/
user guide ? EP387A_ug v0.7 explore microelectronics 19 user guide end sheet free datasheet http://www.datasheetlist.com/
user guide ? EP387A_ug v0.7 explore microelectronics 20 final page of 20 pages free datasheet http://www.datasheetlist.com/

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